VLSI

 

VLSI INTRODUCTION PART MODULE

MODULE 1   : —   INTRODUCTION TO VLSI

  • VLSI Design Flow
  • ASIC Vs FPGA
  • RTL Design Methodologies
  • FPGA Design Flow
  • Introduction to ASIC Verification Methodologies
  • VLSI Design Flow steps
  • Synthesis Versus Simulation

DIGITAL SYSTEM DESIGN MODULE

MODULE 2:—   DIGITAL DESIGN

  • Introduction to digital electronics
  • Arithmetic and data processing units
  • Universal logic elements.
  • Combinational and Sequential Circuits –Design and Analysis.
  • Shift registers and counters.
  • Finite state machine.

HDL MODULE(PROGRAMMING IN XILINX)

MODULE 3:- VERILOG HDL-RTL CODE SYNTHESIS

  • Introduction to Verilog HDL.
  • Gate Level Modelling.
  • Dataflow Modelling.
  • Data Types.
  • Modelling Timing Delays.
  • Abstraction levels.
  • Behavioural Modelling.
  • Parameters, Tasks and Functions.
  • User Defined Primitives.
  • Various Design Examples- Flip flops, ALU etc.

MODULE 4:- FINITE STATE MACHINE

 

  • Basic FSM Structure
  • Mealy Vs Moore
  • Common FSM coding styles

 

FPGA MODULE

 

 

MODULE 5:- FPGA ARCHITECTURE

  • Introduction to programmable logic.
  • Basic Components of FPGA (LUT, CLB, SWITCH MATRIX, IOB).
  • FPGA Configuration MODES.
  • Start Up Sequence.
  • Synthesis Techniques and Implementation Options.
  • Area Planning Using Plan Ahead.
  • Set Up a UCF File Using Floor Planner.
  • Xilinx Tool Flow.
  • Reading reports generated.
  • Module level implementation and verification.
  • Building the top level module
  • Implementing the design onto the FPGA Board.

SIMULATION AND DEBUGGING MODULE

 

MODULE 6:- MODELSIM

  • Introduction to ModelSim Tool.
  • Design and Implementation using Modelsim Simulator.
  • Use ModelSim Commands to run Simulation .
  • Design hierarchy and Simulating Designs.
  • Advantages of ModelSim Tool.

SCHEMATIC CAPTURE MODULE

 

MODULE 7:- XILINX ISE SCHEMATIC CAPTURE TOOL

  • Creating a Xilinx ISE project
  • Using schematic capture to create logic circuits and symbol elements
  • Creating a User Constraints File (UCF)
  • Synthesizing, implementing, and generating a Programming file

 

 

 

MODULE 8:- STATE CAD USING XILINX

  • Draw FSMs
  • Optimize
  • Generate HDL
  • Document
  • Synthesize
  • Test Bench
  • Verify
  • Detect Bugs

MODULE 9:- PlATFORM STUDIO AND EMBEDDED DEVELOPMENT KIT

  • Xilinx Platform Studio
  • Xilinx Software Development Kit
  • The Base System Builder Wizard
  • Feature-rich C/C++ code editor and compilation environment (SDK)

 

 

 

 

 

 

 

HANDS ON EXPERIENCE ON BASYS2 BOARD

 

 

SCHEDULE OF PROGRAMMING EXERCISES USING FPGA BASYS2BOARD

 

VERILOG LAB SESSIONS

VERILOG/VHDL CODES FOR THE FOLLOWING DIGITAL CIRCUITS:-

  • BASIC GATES AND UNIVERSAL GATES
  • HALF AND FULL ADDER.
  • MULTIPLEXOR (2:1, 4:1 USING 2:1, 8:1).
  • DEMULTIPLEXOR (1:8).
  • ENCODER WITH AND WITHOUT PRIORITY (8:3).
  • 3:8 DECODERS.
  • 2 BIT COMPARATOR.
  • LED Blinking
  • BINARY TO GRAY (USING EXOR GATES).
  • JK FLIP FLOP WITH ASYNCHRONOUS RESET.
  • AND T FLIPS FLOP.
  • BINARY COUNTER.
  • Up-Down Counter (Simple 8-bit Counter)
  • Divide by 2 Counter
  • Divide by 3 Counter
  • TRAFFIC LIGHT SIGNAL.

 

Reference Books
We recommend the following books for purchase which will be helpful to you at the time of Our Professional Development Course

  • VHDL – Douglas Perry
  • Verilog HDL – Samir Palnitkar (Indian Edition)
  • Logic and Computer Design Fundamentals 2nd Edition – M. Morris Mano and Charles R. Kime
  • FPGA-Based System Design – Wayne Wolf.

We will be providing our own material and lab books for your daily assignments & practices.